<?xml version='1.0' encoding='UTF-8' standalone='no'?>
<module moduleId="4011_4_x_2_input_NAND_gate_single" referenceFile="4011_4_x_2_input_NAND_gate_single.fzp" fritzingVersion="0.9.3b">
  <version>4</version>
  <author>Stephen G. Parry (modified by vanepp jan 2019)</author>
  <title>4011 4 x 2 Input NAND Gate, single part</title>
  <label>U</label>
  <date>Sun Jun 19 2016</date>
  <tags>
    <tag>DIP</tag>
    <tag>4011</tag>
    <tag>NAND Gate</tag>
    <tag>2 input NAND Gate</tag>
    <tag>logic gates</tag>
    <tag>DIP14</tag>
    <tag>fritzing core</tag>
  </tags>
  <properties>
    <property name="chip label">4011</property>
    <property name="editable pin labels">false</property>
    <property name="variant">4 x 2 Input NAND gate, single part</property>
    <property name="part number">4011</property>
    <property name="family">40xx 4x2 input logic gate (single part)</property>
    <property name="pins">14</property>
    <property name="hole size"/>
    <property name="pin spacing">300mil</property>
    <property name="layer"/>
    <property name="package">DIP (Dual Inline) [THT]</property>
    <property name="devices">4</property>
    <property name="inputs per device">2</property>
  </properties>
  <taxonomy>part.dip.14.pins</taxonomy>
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    <iconView>
      <layers image="icon/40xx_series_DIP14_single_icon.svg">
        <layer layerId="icon"/>
      </layers>
    </iconView>
    <breadboardView>
      <layers image="breadboard/40xx_series_DIP14_breadboard.svg">
        <layer layerId="breadboard"/>
      </layers>
    </breadboardView>
    <schematicView>
      <layers image="schematic/4011_4_x_2_input_NAND_gate_single_schematic.svg">
        <layer layerId="schematic"/>
      </layers>
    </schematicView>
    <pcbView>
      <layers image="pcb/40xx_series_DIP14_pcb.svg">
        <layer layerId="silkscreen"/>
        <layer layerId="copper0"/>
        <layer layerId="copper1"/>
      </layers>
    </pcbView>
  </views>
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      <description>A1</description>
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    <connector id="connector1" name="B1" type="male">
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    </connector>
    <connector id="connector3" name="Q2" type="male">
      <description>Q2</description>
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        <breadboardView>
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          <p svgId="connector3pin" layer="copper1"/>
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      </views>
    </connector>
    <connector id="connector4" name="A2" type="male">
      <description>A2</description>
      <views>
        <breadboardView>
          <p svgId="connector4pin" terminalId="connector4terminal" layer="breadboard"/>
        </breadboardView>
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    <connector id="connector5" name="B2" type="male">
      <description>B2</description>
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    </connector>
    <connector id="connector6" name="GND" type="male">
      <description>GND</description>
      <views>
        <breadboardView>
          <p svgId="connector6pin" terminalId="connector6terminal" layer="breadboard"/>
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    <connector id="connector7" name="A3" type="male">
      <description>A3</description>
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      <description>Q3</description>
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      <description>Q4</description>
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    <connector id="connector11" name="A4" type="male">
      <description>A4</description>
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    <connector id="connector12" name="B4" type="male">
      <description>B4</description>
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        <breadboardView>
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    </connector>
    <connector id="connector13" name="VDD" type="male">
      <description>VDD</description>
      <views>
        <breadboardView>
          <p svgId="connector13pin" terminalId="connector13terminal" layer="breadboard"/>
        </breadboardView>
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    </connector>
  </connectors>
</module>
